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low power mixer/limiter/rssi 3 v receiver if subsystem ad608 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1996C2009 analog devices, inc. all rights reserved. features mixer ?15 dbm, 1 db compression point ?5 dbm ip3 24 db conversion gain >500 mhz input bandwidth logarithmic/limiting amplifier 80 db rssi range 3 phase stability over 80 db range low power 21 mw at 3 v power consumption cmos-compatible power-down to 300 w typical 200 ns enable/disable time applications phs, gsm, tdma, fm, or pm receivers battery-powered instrumentation base station rssi measurements general description the ad608 provides a low power, low distortion, low noise mixer as well as a complete, monolithic logarithmic/limiting amplifier that uses a successive-detection technique. in addition, the ad608 provides both a high speed received signal strength indicator (rssi) output with 80 db dynamic range and a hard-limited output. the rssi output is from a two-pole postdemodulation low-pass filter and provides a loadable output voltage of 0.2 v to 1.8 v. the ad608 operates from a single 2.7 v to 5.5 v supply at a typical power level of 21 mw at 3 v. the rf and local oscillator (lo) bandwidths both exceed 500 mhz. in a typical if application, the ad608 can accept the output of a 240 mhz surface acoustic wave (saw) filter and down- convert it to a nominal 10.7 mhz if with a conversion gain of 24 db (z if = 165 ). the ad608 logarithmic/limiting amplifier section handles any if from low frequency (lf) up to 30 mhz. the mixer is a doubly balanced gilbert-cell mixer and operates linearly for rf inputs spanning ?95 dbm to ?15 dbm. it has a nominal ?5 dbm third-order intercept. an on-board lo pre- amplifier requires only ?16 dbm of lo drive. the current output of the mixer drives a reverse-terminated, industry-standard 10.7 mhz, 330 filter. the nominal logarithmic scaling is such that the output is +0.2 v for a sinusoidal input to the if amplifier of ?75 dbm and +1.8 v at an input of +5 dbm; over this range, the logarithmic confor- mance is typically 1 db. the logarithmic slope is proportional to the supply voltage. a feedback loop automatically nulls the input offset of the first stage down to the submicrovolt level. the ad608 limiter output provides a hard-limited signal output at 400 mv p-p. the voltage gain of the limiting amplifier to this output is more than 100 db. transition times are 11 ns and the phase is stable to within 3 at 10.7 mhz for signals from ?75 dbm to +5 dbm. the ad608 is enabled by a cmos logic-level voltage input, with a response time of 200 ns. when disabled, the standby power is reduced to 300 w within 400 ns. the ad608 is specified for the industrial temperature range of ?25c to +85c for 2.7 v to 5.5 v supplies and ?40c to +85c for 3.0 v to 5.5 v supplies. this device comes in a 16-lead plastic soic. functional block diagram 24db mixer gain 110db limiter gain 90db rssi bias mxop mixer bpf driver vmid lo preamp ad608 rfhi rflo if input ?75dbm to +15dbm 2 ifhi iflo lmop vps2 rssi fdbk com3 final limiter 100nf 10nf 330 ? 50a 330 ? midsupply if bias limiter output 400mv p-p prup rf input ?95dbm to ?15dbm 1 vps1 com1 com2 lohi rssi output 20mv/db 0.2v to 1.8v 3db nominal insertion loss +2.7v to 5.5v 5-stage if amplifier (16db per stage) 7 full-wave rectifier cells 2.7v to 5.5v lo input ?16dbm cmos logic input 6ma max output (890mv into 165 ? ) 100 ? 18nf 1 ?15dbm = 56mv maximum for linear operation. 2 39.76v rms to 397.6mv rms for 1db rssi accuracy. 2mhz lpf 10.7mhz band-pass filter 5 6 1 2 3 4 16 8 7 10 13 9 15 14 12 11 + + + 07886-001 figure 1.
ad608 rev. c | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 4 ? thermal resistance ...................................................................... 4 ? esd caution .................................................................................. 4 ? pin configuration and function descriptions ............................. 5 ? typical performance characteristics ............................................. 6 ? test circuits ....................................................................................... 8 ? theory of operation ........................................................................ 9 ? mixer ...............................................................................................9 ? mixer gain .....................................................................................9 ? if filter terminations ................................................................ 10 ? the logarithmic if amplifier .................................................. 10 ? offset feedback loop ................................................................ 10 ? rssi output ................................................................................ 11 ? digitizing the rssi ..................................................................... 11 ? power consumption .................................................................. 11 ? troubleshooting .......................................................................... 11 ? applications information .............................................................. 12 ? outline dimensions ....................................................................... 13 ? ordering guide .......................................................................... 13 ? revision history 2/09rev. b to rev. c updated format .................................................................. universal reorganized layout ............................................................ universal change to general description section ........................................ 1 changes to dc level parameter, operating range parameter, and t min to t max parameter, table 1 .......................................... 3 added typical performance characteristics heading ................ 6 added test circuits heading .......................................................... 8 changes to figure 17 and figure 19 ............................................... 8 change to figure 22 ......................................................................... 9 changes to table 5 ............................................................................ 9 updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 13
ad608 rev. c | page 3 of 16 specifications t a = 25c, supply = 3 v, dbm is referred to 50 , unless otherwise noted. table 1. parameter conditions 1 min typ max unit mixer performance rf and lo frequency range 500 mhz lo power input terminated in 50 ?16 dbm conversion gain driving doubly terminated 330 if filter, z if = 165 19 24 28 db noise figure matched input, f rf = 100 mhz 11 db matched input, f rf = 240 mhz 16 db 1 db compression point input terminated in 50 ?15 dbm third-order intercept f rf = 240 mhz and 240.02 mhz, f lo = 229.3 mhz ?5 dbm input resistance f rf = 100 mhz (see table 5 ) 1.9 k input capacitance f rf = 100 mhz (see table 5 ) 3 pf limiter performance gain full temperature and supply range 110 db limiting threshold 3 rms phase jitter at 10.7 mhz ?75 dbm 280 khz if bandwidth input resistance 10 k input capacitance 3 pf phase variation ?75 dbm to +5 dbm if input signal at 10.7 mhz 3 degrees dc level center of output swing (vpos C 1 v) 2 v output level limiter output driving 5 k load 400 mv p-p rise and fall times driving a 5 pf load 11 ns output impedance 200 rssi performance at 10.7 mhz nominal slope at vpos = 3 v; proportional to vpos 17.27 20 23.27 mv/db nominal intercept ?85 dbm minimum rssi voltage ?75 dbm input signal 0.2 v maximum rssi voltage +5 dbm input signal 1.8 v rssi voltage intercept 0 dbm input signal 1.57 1.82 v logarithmic linearity error ?75 dbm to +5 dbm input signal at ifhi 1 db rssi response time 90% rf to 50% rssi 200 ns output impedance at midscale 250 power-down interface logic threshold system active on logic high 1.5 v input current for logic high 75 ma power-up response time active limiter output 200 ns power-down response time to 200 a supply current 400 ns power-down current 100 a power supply operating range ?25c to +85c 2.7 5.5 v ?40c to +85c 3.0 5.5 v powered up current vpos = 3 v 7.3 ma operating temperature t min to t max vpos = 2.7 v to 5.5 v ?25 +85 c vpos = 3.0 v to 5.5 v ?40 +85 c 1 vpos is used to refer collectively to the vps1 and vps2 pins.
ad608 rev. c | page 4 of 16 absolute maximum ratings table 2. parameter rating supply voltages vps1, vps2 +6 v internal power dissipation 600 mw temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. package type ja unit 16-lead soic 110 c/w esd caution
ad608 rev. c | page 5 of 16 pin configuration and fu nction descriptions vps1 com1 prup lmop rfhi rflo mxop com3 rssi iflo lohi com2 vps2 fdbk ifhi vmid 1 2 3 4 16 15 14 13 5 12 6 11 7 10 8 9 ad608 top view (not to scale) 07886-002 figure 2. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vps1 1 positive supply input 2 com1 common 3 lohi local oscillator input connection 4 com2 common 5 rfhi rf input, noninverting 6 rflo rf input, inverting 7 mxop mixer output 8 vmid midpoint supply bias output 9 ifhi if input, noninverting 10 iflo if input, inverting 11 rssi received signal strength indicator output 12 com3 output common 13 fdbk offset-null feedback loop output 14 vps2 1 limiter positive supply input 15 lmop limiter output 16 prup power-up 1 vpos is used to refer collectively to the vps1 and vps2 pins in this data sheet.
ad608 rev. c | page 6 of 16 typical performance characteristics rf frequency (mhz) mixer conversion gain (db) 25.0 23.5 22.0 500 50 0 100 150 200 250 300 350 400 450 24.5 24.0 23.0 22.5 07886-005 figure 3. mixer conversion gain vs. rf frequency if frequency (mhz) mixer response (db) 0 ?8 80 10 0 20 30 40 50 60 70 ?1 ?4 ?5 ?6 ?7 ?2 ?3 07886-006 figure 4. mixer if port bandwidth input power at ifhi (dbm) rssi output (v) 3.0 0 10 ?70 ?80 ?60 ?50 ?40 0 ?20 ?10 ?30 2.5 2.0 1.5 1.0 0.5 5v 3v 0 7886-007 figure 5. if rssi output vs. input power at ifhi and supply voltage, ambient temperature (see figure 15 ) input power (dbm) rssi output (v) 3.0 0 2.5 2.0 1.5 1.0 0.5 +85c +25c ?25c 10 ?70?80 ?60 ?50 ?40 0 ?20 ?10 ?30 0 7886-008 figure 6. if rssi output vs. input power and temperature, 3 v supply (see figure 15 ) input power (dbm) rssi error (db) 4 ?4 10 ?80 ?70 ?50 0 ?60 ?40 ?20 ?10 ?30 3 0 ?1 ?2 ?3 2 1 5v 3v 07886-010 figure 7. rssi error vs. input power (see figure 15 ) prup rssi 0 7886-011 100ns/div 800mv/div 100ns/div 1v/div figure 8. rssi power-up response (see figure 19 )
ad608 rev. c | page 7 of 16 rssi ifhi 07886-013 200mv/div 800mv/div 50ns/div figure 9. rssi pulse response/rssi rise time (see figure 16 ) lmop 07886-015 20ns/div 60mv/div figure 10. limiter rise and fall times (see figure 20 ) prup lmop 0 7886-017 220mv/div 100ns/div 100ns/div 1v/div figure 11. limiter power-up response time (see figure 17 ) input power at ifhi (dbm) 5 ?5 4 ?1 ?2 ?3 ?4 3 2 0 1 limiter phase (degrees) 10 ?80 ?70 ?50 0 ?60 ?40 ?20 ?10 ?30 0 7886-019 figure 12. limiter phase performance vs. input power at ifhi (see figure 21 ) input power at ifhi (dbm) 10 0 9 4 3 2 1 8 7 5 6 limiter rms jitter (degrees) 10 ?80 ?70 ?50 0 ?60 ?40 ?20 ?10 ?30 0 7886-021 figure 13. limiter rms jitter performance vs. input power at ifhi (see figure 21 )
ad608 rev. c | page 8 of 16 test circuits prup input vpos 51. 1 ? 51.1 ? 0.1f 1nf 1nf 332 ? 0.1f 332 ? 301 ? 54.9 ? if input 0.1f 10nf rssi output 100 ? 18nf 0.1f lmop output trigger 4.7k ? u1 ? 74hc00 0.1f u1a u1b 47k ? 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad608 vps1 com1 rfhi rflo mxop lohi com2 vmid prup lmop com3 rssi iflo vps2 fdbk ifhi 0 7886-003 figure 14. if test board schematic ifhi vpos rssi if test board 10.7mhz fluke 6082a synthesizer dcps dc power supply (dcps) 3v agilent hp3366a dmm digital multimeter (dmm) agilent hp34401a 07886-009 figure 15. test circuit for if rssi output vs. input power at ifhi and supply voltage, ambient temperature ( figure 5 ); if rssi output vs. input power and temperature, 3 v supply ( figure 6 ); and rssi error vs. input power ( figure 7 ) ifhi vpos rssi if test board agilent hp3366a fet probe tekronix p6201 ch 1 ch 2 coupler mcl zdc-20-1 agilent hp54120a digital oscilloscope 3v dcps 10.7mhz 0dbm fluke 6082a synthesizer 07886-014 figure 16. test circuit for rssi pulse response/rssi rise time ( figure 9 ) ifhi vpos lmop if test board 3v agilent hp3366a tekronix p6201 prup ch 1 ch 2 agilent hp54120a digital oscilloscope dcps 10.7mhz 0dbm fluke 6082a synthesizer fet probe 07886-018 figure 17. test circuit for limiter power-up response time ( figure 11 ) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad608 vps1 com1 rfhi rflo mxop lohi com2 vmid prup lmop com3 rssi iflo vps2 fdbk ifhi vpos lo input rf input if output nc nc 0.1f 1nf 51.1 ? 1nf 332 ? 301 ? 0.1f 54.9 ? 51.1 ? 1nf 0.1f 332 ? 10nf 100 ? 18nf 18nf 47k ? nc = no connect 0 7886-004 figure 18. mixer te st board schematic ifhi vpos rssi if test board 10.7mhz 0dbm fluke 6082a synthesizer dcps agilent hp3366a fet probe tekronix p6201 prup ch 1 ch 2 a gilent hp54120a digital oscilloscope 3v 07886-012 figure 19. test circuit for rssi power-up response ( figure 8 ) ifhi vpos lmop if test board 10.7mhz 0dbm fluke 6082a synthesizer dcps agilent hp3366a fet probe tekronix p6201 a gilent hp54120a digital oscilloscope 3v 07886-016 figure 20. test circuit for limiter rise and fall times ( figure 10 ) ifhi rssi if test board 10.7mhz fluke 6082a s ynthesizer dcps 3v agilent hp3366a fet probe tektronix p6201 ch 1 trig agilent hp54120a digital oscilloscope mcl zdc-20-1 bpf agilent hp8447a agilent hp8494a hp8495a 280khz bw 10.7mhz cf toko sk107mk1-a0-10 coupler 07886-020 figure 21. test circuit for limiter phase performance vs. input power at ifhi ( figure 12 ) and limiter rms jitter performance vs. input power at ifhi ( figure 13)
ad608 rev. c | page 9 of 16 theory of operation the ad608 consists of a mixer followed by a logarithmic if strip with rssi and hard-limited outputs (see figure 22 ). mixer the mixer is a doubly balanced, modified gilbert-cell mixer. its maximum input level for linear operation is either 56.2 mv, regardless of the impedance across the mixer inputs, or ?15 dbm for a 50 input termination. the input impedance of the mixer can be modeled as a simple parallel rc network; the resistance and capacitance values vs. frequency are listed in table 5 . the bandwidth from the rf input to the if output at the mxop pin is ?1 db at 30 mhz and then rapidly decreases as frequency increases (see figure 4 ). mixer gain the conversion gain of the mixer is the product of its trans- conductance and the impedance seen at pin mxop. for a 330 parallel-terminated filter at 10.7 mhz, the load impedance is 165 , the gain is 24 db, and the output is 15.85 56.2 mv (or 891 mv) centered on the midpoint of the supply voltage. for other load impedances, the expression for the gain in decibels is g db = 20 log 10 (0.0961 r l ) where: g db is the gain in decibels. r l is the load impedance at pin mxop. the gain of the mixer can be increased or decreased by changing r l . the limitations on the gain are the 6 ma maximum output current at mxop and the maximum allowable voltage swing at pin mxop, which is 1.0 v for a 3 v supply or 5 v supply. 24db mixer gain 110db limiter gain 90db rssi bias mxop mixer bpf driver vmid lo preamp ad608 rfhi rflo if input ?75dbm to +15dbm 2 ifhi iflo lmop vps2 rssi fdbk com3 final limiter 100nf 10nf 330 ? 50a 330 ? midsupply if bias limiter output 400mv p-p prup rf input ?95dbm to ?15dbm 1 vps1 com1 com2 lohi rssi output 20mv/db 0.2v to 1.8v 3db nominal insertion loss 2.7v to 5.5v 5-stage if amplifier (16db per stage) 7 full-wave rectifier cells 2.7v to 5.5v lo input ?16dbm cmos logic input 6ma max output (890mv into 165 ? ) 100 ? 18nf 1 ?15dbm = 56mv maximum for linear operation. 2 39.76v rms to 397.6mv rms for 1db rssi accuracy. 2mhz lpf 10.7mhz band-pass filter 5 6 1 2 3 4 16 8 7 10 13 9 15 14 12 11 + + + 07886-022 figure 22. functional block diagram table 5. mixer input impedance vs. frequency frequency (mhz) resistance () capacitance (pf) 45 2800 3.1 70 2600 3.1 100 1900 3.0 200 1200 3.1 300 760 3.2 400 520 3.4 500 330 3.6
ad608 rev. c | page 10 of 16 if filter terminations the ad608 was designed to drive a parallel-terminated 10.7 mhz band-pass filter (bpf) with a 330 impedance. with a 330 parallel-terminated filter, pin mxop sees a 165 termination, and the gain is nominally 24 db. other filter impedances and gains can be accommodated by either accepting an increase or decrease in gain in proportion to the filter impedance or by keeping the impedance seen by mxop at a nominal 165 (by using resistive dividers or matching networks). figure 23 shows a simple resistive voltage divider for matching an assortment of filter impedances, and tabl e 6 lists component values. the logarithmic if amplifier the logarithmic if amplifier consists of five amplifier stages of 16 db gain each, plus a final limiter. the if bandwidth is 30 mhz (?1 db), and the limiting gain is 110 db. the phase skew is 3 from ?75 dbm to +5 dbm (approximately 111 v p-p to 1.1 v p-p). the limiter output impedance is 200 , and the limiter output drive is 200 mv (400 mv p-p) into a 5 k load. in the absence of an input signal, the limiter output limits noise fluctuations, producing an output that continues to swing 400 mv p-p, but with random zero crossings. offset feedback loop because the logarithmic amplifier is dc-coupled and has more than 110 db of gain from the input to the limiter output, a dc offset at its input of even a few microvolts causes the output to saturate. therefore, the ad608 uses a low frequency feedback loop to null the input offset. referring to figure 23 , the loop consists of a current source driven by the limiter, which sends 50 a current pulses to pin fdbk. the pulses are low-pass filtered by a -network consisting of c1, r4, and c5. the smoothed dc voltage that results is subtracted from the input to the if amplifier at pin iflo. because this is a high gain amplifier with a feedback loop, care should be taken in layout and component values to prevent oscillation. recommended values for the common ifs of 450 khz, 455 khz, 6.5 mhz, and 10.7 mhz are listed in table 6 . 5v c2 100pf 47k ? 24db mixer gain 110db limiter gain 90db rssi bias mxop mixer bpf driver vmid lo preamp ad608 rfhi rflo ifhi iflo lmop vps2 rssi fdbk com3 final limiter 100nf c5 r1 50a r3 midsupply if bias prup vps1 com1 com2 lohi 12db nominal insertion loss (assumes 6db in filter) 5-stage if amplifier (16db per stage) 7 full-wave rectifier cells lo input ?16dbm cmos logic input r4 c1 2mhz lpf band-pass filter 5 6 1 2 3 4 16 8 7 10 13 9 15 14 12 11 r2 + + + c1 1f 07886-023 figure 23. applications diagram fo r common ifs and filter impedances table 6. ad608 filter termination an d offset-null feedback loop resistor and capacitor values for common ifs if filter impedance filter termination resistor values 1 for 24 db of mixer gain offset-null feedback loop values r1 r2 r3 r4 c1 c5 450 khz 2 1500 174 1330 1500 1000 200 nf 100 nf 455 khz 1500 174 1330 1500 1000 200 nf 100 nf 6.5 mhz 1000 178 825 1000 100 18 nf 10 nf 10.7 mhz 330 330 0 330 100 18 nf 10 nf 1 resistor values were calculated so that r1 + r2 = z filter and r1||(r2 + z filter ) = 165 . 2 operation at ifs of 450 khz and 455 khz requires use of an exte rnal low-pass filter with at least one pole at a cutoff frequen cy of 90 khz (a decade below the ripple at 900 khz).
ad608 rev. c | page 11 of 16 rssi output the logarithmic amplifier uses a successive-detection architecture. each of the five stages has a full-wave detector; two additional high level detectors are driven by attenuators at the input to the limiting amplifiers, for a total of seven detector stages. because each detector is a full-wave rectifier, the ripple component in the resulting dc is at twice the if. the ad608 low-pass filter has a 2 mhz cutoff frequency, which is one decade below the 21.4 mhz ripple that results from a 10.7 mhz if. for operation at lower ifs, such as 450 khz or 455 khz, the ad608 requires an external low-pass filter with a single pole located at 90 khz, a decade below the 900 khz ripple frequency for these ifs. the rssi range is from the noise level at approx- imately ?80 dbm to overload at +15 dbm and is specified for 1 db accuracy from ?75 dbm to +5 dbm. the +15 dbm maximum if input is provided to accommodate band-pass filters of lower insertion loss than the nominal 4 db for 10.7 mhz ceramic filters. digitizing the rssi in typical cellular radio applications, the rssi output of the ad608 is digitized by an analog-to-digital converter (adc). the rssi output of the ad608 is proportional to the power supply voltage, which not only allows the adc to use the supply as a reference, but also causes the rssi output and the adc output to track over power supply variations, reducing system errors and component costs. power consumption the total power supply current of the ad608 is a nominal 7.3 ma. the power is signal dependent, partly because the rssi output increases (the current is increased by 200 a at an rssi output of +1.8 v), but mostly due to the if consumption of the band-pass filter when driven to 891 mv, assuming a 4 db loss in this filter and a peak input of +5 dbm to the log-if amp. in addition, the power is temperature dependent because the biasing system used in the ad608 is proportional to the absolute temperature (ptat). troubleshooting the most common causes of problems with the ad608 are incorrect component values for the offset feedback loop, poor board layout, and pickup of radio frequency interference (rfi), which all cause the ad608 to lose the low end (typically below ?65 dbm) of its rssi output and cause the limiter to swing randomly. both poor board layout and incorrect component values in the offset feedback loop can cause low level oscillations. pickup of rfi can be caused by improper layout and shielding of the circuit.
ad608 rev. c | page 12 of 16 applications information figure 24 shows the ad608 configured for operation in a digital system at a 10.7 mhz if. the input and output impedance of the filter are parallel terminated using 330 resistors, and the conversion gain is 24 db. the rf port is terminated in 50 ; in a typical application, the input is matched to a saw filter using the impedance data provided in table 5 . figure 25 shows the ad608 configured for narrow-band fm operation at a 450 khz or 455 khz with an external discriminator. the if filter has 1500 input and output impedancesthe input is matched via a resistive divider, and the output is terminated in 1500 . the discriminator requires a 1 v p-p drive from a 1 k source impedance, which in figure 25 is provided by a class a amplifier with a gain of 2.5. 10.7mhz bpf z = 330 ? r2 330 ? c5 0.1f r1 330 ? c2 100pf c3 100pf c4 100pf c1 1f v pos limo c6 10nf supply 2.7v to 5.5v power-up 3v cmos lo input ?16dbm rf input ?95dbm to ?15dbm c7 18nf 16 15 12 11 10 14 13 9 1 2 5 6 7 3 4 8 ad608 vps1 com1 rfhi rflo mxop lohi com2 vmid prup lmop com3 rssi iflo vps2 fdbk ifhi r3 100 ? r4 47k ? r6 51.1 ? r5 51.1 ? limiter output vpos ?1v 200mv rssi output +0.2v to +1.8v (20mv/db) + + + + + + + 07886-024 offset-control loop filter bpf temination if bias point decoupling bpf reverse termination bias point at vpos/2 figure 24. application at 10.7 mhz (the band-pass filter can be a toko sk107 or murata sfe10.7) +5v r1 51.1 ? r2 51.1 ? c1 0.1f c2 1nf gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad608 vps1 com1 rfhi rflo mxop lohi com2 vmid prup lmop com3 rssi iflo vps2 fdbk ifhi r3 374? r4 1.5k ? r6 1k? lohi rfhi c3 1nf r7 1130 ? f1 c7 0.1f c6 0.1f c8 0.1f c9 0.2f r5 200 ? c5 0.1f r14 8.66k ? r15 24.9k ? r13 402 ? r12 1k? cr1 cr2 r8 1k? r9 1k? c10 0.01f r11 3.3k ? audio prup rssi jumpe r f1: toko hcfm2?455b f2: murata cfy455s cr1, cr2: 1n60 q1: 2n3906 f2 r10 3.3k ? r16 47k? q1 c11 0.1f c4 1nf 07886-025 figure 25. narrow-band fm application at 450 khz or 455 khz
ad608 rev. c | page 13 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 26. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches) ordering guide model temperature range packag e description package option ad608ar ?40c to +85c 16-lead standard small outline package [soic_n] r-16 ad608ar-reel ?40c to +85c 16-lead standard small outline package [soic_n] r-16 AD608ARZ 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 AD608ARZ-rl 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 eval-ad608ebz 1 evaluation board 1 z = rohs compliant part.
ad608 rev. c | page 14 of 16 notes
ad608 rev. c | page 15 of 16 notes
ad608 rev. c | page 16 of 16 notes ?1996C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07886-0-2/09(c)

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